Absolute Encoder Interfaces for Brushless Motors

This paper discusses absolute encoder interfaces commonly used in brushless motor control systems. The concept of encoder latency is presented. SSI, BiSS-C®, DRIVE-CliQ and several versions of HIPERFACE® and EnDat are reviewed. The paper concludes with a comparison chart to help select the appropriate interface.

Encoder Latency and Cycle Time

When using absolute encoders for brushless motor feedback it is important to consider encoder latency. Encoder latency is defined by the time required to capture and process position data plus the serial communication transmission time. With the high speed of modern interfaces, transmission time is a minor consideration. Position capture and process time, varies significantly by manufacturer. Larger latencies (> 50 usec) affect servoloop phase margins resulting in compromised dynamic response. The higher bandwidth velocity loop is particularly affected.

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Fig. 1

Cycle time represents how frequently the encoder can be read by the drive. Cycle time includes encoder latency and any recovery time after data transmission. Encoder manufacturers may specify position capture/process time or cycle time or both. Cycle time depends on the amount of data transmitted. It is typically specified assuming the smallest possible data packet.

Encoder Memory and Digital Nameplate

Encoders with bidirectional serial interfaces allow access to internal memory. The memory typically incorporates the following parameter sets:

  • Configuration: encoder manufacturer specifications such as resolution, frame content
  • Operating: position information and temperature (if a sensor is connected)
  • Status: warnings, errors, diagnostics
  • OEM: motor parameters (poles, resistance, inductance, commutation offset etc.)

The content and format of OEM parameter memory is defined so that the information can be read by specific servo drives for plug-and-play current loop configuration and brushless motor commutation.


Serial Synchronous Interface (SSI) is a loose standard with many versions of frame content. Incremental sin/cos or A/B signals are optional as SSI is relatively slow at 1.5 Mbps, and communication latency can be an issue. The communication technique of SSI is common to several serial interfaces. In default mode, the encoder continuously tracks position. The drive initiates a series of clock pulses (shown in Fig.1), to read the encoder. The position data is latched into the output register and then clocked out on the data line. The drive continues to generate clock pulses until all data in the output register have been transmitted.

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Fig. 2

SSI is unidirectional, so the drive cannot read or write to the encoder registers. Some versions include a CRC (cyclic redundancy check) or parity bits in the frame. Double data transmissions may be used to improve communication integrity. The physical layer is RS-422 or RS-485 twisted pair.

Propagation Delay Compensation

A serial synchronous interface employs a clock signal to clock out data from the encoder output register. The same clock signal is used to clock data into the drive input register. The propagation delay between the clock transition at the drive output to data subsequently received at the drive input must be considered. For a 100-meter cable this delay is 1 μsec. At a 10 Mbps clock rate the clock and data are out of synchronization by 10 bits.

Some serial interfaces incorporate propagation delay compensation. During initialization the drive measures the delay between the clock at the drive, and the data received. During subsequent operation the drive waits the appropriate number of clocks so that synchronization is reestablished before sampling the data. This technique facilitates much faster clock rates.


BiSS-C is an open standard employing a synchronous clocking technique. A BiSS-C master employs propagation delay compensation so faster clocking is possible, up to 20 Mbps depending on cable length. BP3, is a subset of BiSS-C defining the frame content for encoders. The frame includes a CRC and error/warning bits. The diagnostics which generate error/warning depend on the encoder manufacturer. Note that BiSS-C is not compatible with the older BiSS-B standard.

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Fig. 3

BiSS-C facilitates encoder register access by using the logic state of the clock line during the frame timeout as a bit (CDM) for control and data. Only one CDM bit is available each cycle so multiple cycles are required to send a command, a register address, and the data. The encoder also inserts one bit of register data into the frame per cycle so that data can be read over multiple cycles. This technique is relatively complex, but there is a significant benefit in reduced latency as parameters can be exchanged without interrupting position data transmission.

Point-to-point BiSS-C is typically used in brushless motor applications, but bussing is also supported. This capability may be of value in a robot joint with one encoder on the motor, and another encoder on the output of the gearbox. One cable can be routed to the joint but the encoders must be daisy-chained as shown in Fig. 4. Each encoder receives the clock simultaneously. Data-Out (SLO) of Encoder A is connected to the Data-In (SLI) of Encoder B and combined into one continuous frame which is clocked out of Encoder B.

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Fig. 4

BP3S, a version of BP3, supports Functional Safety. BP3S supports redundant position measurement. It incorporates a working counter in the frame to track the number of communication instances recognized by the encoder. The working counter from the encoder is compared to a working counter in the drive to verify that no communication instances have been lost.

EnDat 2.2

EnDat 2.2 is a proprietary interface for HEIDENHAIN encoders. Like BiSS-C, the data is clocked synchronously but register access is handled differently. As can be seen in Fig. 5, the data line is bidirectional. The type of data to be transmitted from the encoder is first defined by a mode command from the drive. Data can be a position value, register data, or a position value plus register data (Fig. 5).

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EnDat 2.2 encoders have extensive diagnostics. Redundant error bits are included in the frame and a CRC is appended to each data packet. Communication is point-to-point over an RS-485 physical layer. Clock frequency is 2 Mbps. If the drive supports propagation delay compensation, 16 Mbps is possible. As shown in Fig. 5, an additional pair of wires are provided for battery backup or for use as power supply sense lines. EnDat 2.2 supports Functional Safety.

EnDat 3

EnDat 3 is an open standard which can be licensed from HEIDENHAIN. EnDat 3 employs a half-duplex communication scheme over RS-485. A communication cycle consists of a request from the drive followed by a response from the encoder as shown in Fig.6. Request and response each have a preamble (PRE) and a postamble (POST) which includes a CRC.

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Fig. 6

The response has a high priority frame (HPF) for position information and optional low priority frames (up to 15) for encoder register data and redundant Functional Safety information. The number and content of LPFs is preconfigured and described by the low priority header (LPH). Data rate is 12.5 Mbps (100 m cable) or 25 Mbps (40 m cable).

EnDat 3 uses two wires for communication and typically has two additional wires for encoder power. The digital data stream, however, has no DC component and can be modulated onto the supply lines for a 2-wire solution. The transmit and receive circuitry becomes more complex as transformers are required for modulation. Although it is possible to connect EnDat 3 encoders on a bus, it is not common in brushless motor control.


HIPERFACE is a proprietary interface for SICK encoders. HIPERFACE employs an asynchronous half duplex serial interface to read absolute position at startup and to read/write encoder memory. The serial interface is also used to communicate errors via an error code transmitted by the encoder.

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Fig. 7

As shown in Fig. 7 HIPERFACE includes sin/cos incremental signals. After the initial absolute position reading, the drive tracks incremental sin/cos signals. At 38.4 Kbps it is not practical to read position via the serial interface. Using incremental signals eliminates encoder latency, but the analog signals must be converted to digital data and interpolated in the drive which adds a small delay. HIPERFACE can be used in safety systems, but only safety functions based on position increments derived from the sin/cos signals are available.


HIPERFACE DSL is an open standard which can be licensed from SICK. DSL operates in two ways:

  • Free Running Mode: – position data are sampled and transmitted immediately
  • SYNC Mode: – position data are sampled and transmitted synchronously with a clock signal

SYNC Mode is typically used in brushless motor control. DSL employs a half-duplex communication scheme over RS-485 as shown in Fig.8. The clock can be considered a synchronous request from the drive. The encoder response is the incremental position change plus optional preconfigured extra data packets. The data rate is 10 Mbps for a 100 m cable.

DSL uses the concept of data channels. The Process Data channel contains the incremental position change. It is transmitted in every response. The channels outlined below transfer data over multiple response cycles in the extra packages.

  • Safe Position 1: absolute position, errors, warnings
  • Safe Position 2: redundant position for Functional Safety only
  • Parameters: configuration, digital nameplate, encoder temperature
  • Sensor Hub: external sensors – temperature, accelerometer
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Fig. 8

HIPERFACE DSL uses two wires for communication. Like EnDat 3, the digital data stream is modulated onto the supply lines. This concept was pioneered by SICK for encoder data transmission. The 2-wire interface can be integrated into the motor cable, but a DSL-rated cable must be used. Although it is possible to connect DSL encoders on a bus, it is not common in brushless motor control.


DRIVE-CLiQ is an open standard which can be licensed from Siemens. DRIVE-CLiQ brings all the flexibility and speed of Ethernet to encoder interfaces – 100 Mbps, bidirectional, point-to-point, bussing, Functional Safety. The details of the Ethernet protocol are beyond the scope of this paper.

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Fig. 9

Encoder Interface Comparison

The table in Fig. 10 shows a comparison of encoder interfaces. The capabilities of BiSS-C, EnDat 3, and HIPERFACE DSL are quite similar, and they all support Functional Safety. Each are open standards, but EnDat 3 and HIPERFACE DSL have licensing costs. The lower performance SSI is an older standard considered a legacy interface by some encoder manufacturers. HIPERFACE is being displaced by HIPERFACE DSL in new designs. EnDat 2.2 is still widely used but is expected to be displaced by the emerging EnDat 3. DRIVE-CliQ is most often seen in Siemens-based systems.

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Fig. 10